#include "idt.h"
#include <stdlib.h>
#include "cpu/irq.h"
#include "ports.h"

static_assert(sizeof(IDT::Pointer) == 6);
constexpr uint8_t irq_base = 0x20;

__attribute__((section(".constinit"))) static IDT::Entry table[256];
static InterruptHandler* handlers[256] = {nullptr};

bool IDT::install(uint8_t irq, InterruptHandler* h) {
  if (h != nullptr && handlers[irq + irq_base] == nullptr) {
    handlers[irq + irq_base] = h;
    return true;
  }
  return false;
}
bool IDT::uninstall(uint8_t irq, InterruptHandler* h) {
  if (handlers[irq + irq_base] == h) {
    handlers[irq + irq_base] = nullptr;
    return true;
  }
  return false;
}

/* reinitialize the PIC controllers, giving them specified vector offsets
   rather than 8h and 70h, as configured by default */

#define ICW1_ICW4 0x01      /* ICW4 (not) needed */
#define ICW1_SINGLE 0x02    /* Single (cascade) mode */
#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
#define ICW1_LEVEL 0x08     /* Level triggered (edge) mode */
#define ICW1_INIT 0x10      /* Initialization - required! */

#define ICW4_8086 0x01       /* 8086/88 (MCS-80/85) mode */
#define ICW4_AUTO 0x02       /* Auto (normal) EOI */
#define ICW4_BUF_SLAVE 0x08  /* Buffered mode/slave */
#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
#define ICW4_SFNM 0x10       /* Special fully nested (not) */


extern "C" uint32_t handle_interrupt(cpu_state_t* r) {
  if (r->irq < irq_base) return reinterpret_cast<uint32_t>(r);

  if (handlers[r->irq] != nullptr) {
    r = handlers[r->irq]->trigger(r);
  }

  pic1_t pic1;
  pic1.write(0x20);
  if (r->irq > irq_base + 7) {
    pic2_t pic2;
    pic2.write(0x20);
  }

  return reinterpret_cast<uint32_t>(r);
};

IDT::IDT(const uint16_t selector) {
  table[0x00] = Entry(&exception0x00, selector, Intr);
  table[0x01] = Entry(&exception0x01, selector, Intr);
  table[0x02] = Entry(&exception0x02, selector, Intr);
  table[0x03] = Entry(&exception0x03, selector, Intr);
  table[0x04] = Entry(&exception0x04, selector, Intr);
  table[0x05] = Entry(&exception0x05, selector, Intr);
  table[0x06] = Entry(&exception0x06, selector, Intr);
  table[0x07] = Entry(&exception0x07, selector, Intr);
  table[0x08] = Entry(&exception0x08, selector, Intr);
  table[0x09] = Entry(&exception0x09, selector, Intr);
  table[0x0a] = Entry(&exception0x0a, selector, Intr);
  table[0x0b] = Entry(&exception0x0b, selector, Intr);
  table[0x0c] = Entry(&exception0x0c, selector, Intr);
  table[0x0d] = Entry(&exception0x0d, selector, Intr);
  table[0x0e] = Entry(&exception0x0e, selector, Intr);
  table[0x0f] = Entry(&exception0x0f, selector, Intr);
  table[0x10] = Entry(&exception0x10, selector, Intr);
  table[0x11] = Entry(&exception0x11, selector, Intr);
  table[0x12] = Entry(&exception0x12, selector, Intr);
  table[0x13] = Entry(&exception0x13, selector, Intr);

  table[0x20] = Entry(&interrupt0x00, selector, Intr);
  table[0x21] = Entry(&interrupt0x01, selector, Intr);
  table[0x22] = Entry(&interrupt0x02, selector, Intr);
  table[0x23] = Entry(&interrupt0x03, selector, Intr);
  table[0x24] = Entry(&interrupt0x04, selector, Intr);
  table[0x25] = Entry(&interrupt0x05, selector, Intr);
  table[0x26] = Entry(&interrupt0x06, selector, Intr);
  table[0x27] = Entry(&interrupt0x07, selector, Intr);

  table[0x28] = Entry(&interrupt0x08, selector, Intr);
  table[0x29] = Entry(&interrupt0x09, selector, Intr);
  table[0x2a] = Entry(&interrupt0x0a, selector, Intr);
  table[0x2b] = Entry(&interrupt0x0b, selector, Intr);
  table[0x2c] = Entry(&interrupt0x0c, selector, Intr);
  table[0x2d] = Entry(&interrupt0x0d, selector, Intr);
  table[0x2e] = Entry(&interrupt0x0e, selector, Intr);
  table[0x2f] = Entry(&interrupt0x0f, selector, Intr);

  pic1_t pic1;
  pic2_t pic2;

  pic1.write(ICW1_INIT | ICW1_ICW4);
  pic2.write(ICW1_INIT | ICW1_ICW4);
  pic1.write(0x20, 0x1);  // offset 0x20
  pic2.write(0x28, 0x1);  // offset 0x28
  pic1.write(0x04, 0x1);  // tell master pic there is a slave pic
  pic2.write(0x02, 0x1);  // tell slave pic its cascade identity

  pic1.write(ICW4_8086, 0x1);
  pic2.write(ICW4_8086, 0x1);

  // pic masks
  pic1.write(0xfc, 0x1);  // only enable irq1
  pic2.write(0xff, 0x1);

  Pointer ptr{.limit = sizeof(table), .base = reinterpret_cast<uint32_t>(table)};
  asm volatile("lidt %0" : : "m"(ptr));

  printk("IDT installed at ", uhex{ptr.base}, '\n');
}