#include "idt.h"
#include <stdlib.h>
#include "ports.h"

static_assert(sizeof(IDT::Pointer) == 6);
// size of IDT::Entry in protected mode is 64 bits
// and in long mode is 128 bits
static_assert(sizeof(IDT::Entry) == 8);

/* reinitialize the PIC controllers, giving them specified vector offsets
   rather than 8h and 70h, as configured by default */

#define ICW1_ICW4 0x01      /* ICW4 (not) needed */
#define ICW1_SINGLE 0x02    /* Single (cascade) mode */
#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
#define ICW1_LEVEL 0x08     /* Level triggered (edge) mode */
#define ICW1_INIT 0x10      /* Initialization - required! */

#define ICW4_8086 0x01       /* 8086/88 (MCS-80/85) mode */
#define ICW4_AUTO 0x02       /* Auto (normal) EOI */
#define ICW4_BUF_SLAVE 0x08  /* Buffered mode/slave */
#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
#define ICW4_SFNM 0x10       /* Special fully nested (not) */

IDT::IDT() {
  pic1_t pic1;
  pic2_t pic2;

  const auto mask1 = pic1.read(0x1);
  const auto mask2 = pic2.read(0x1);

  pic1.write(ICW1_INIT | ICW1_ICW4);
  pic2.write(ICW1_INIT | ICW1_ICW4);
  pic1.write(0x20, 0x1);  // offset 0x20
  pic2.write(0x28, 0x1);  // offset 0x28
  pic1.write(4, 0x1);     // tell master pic there is a slave pic
  pic2.write(2, 0x1);     // tell slave pic its cascade identity
  pic1.write(ICW4_8086, 0x1);
  pic2.write(ICW4_8086, 0x1);

  pic1.write(mask1);
  pic2.write(mask2);

  table[32] = Entry((unsigned long)kirq<0x0>, 0x08, InterruptGate);
  table[33] = Entry((unsigned long)kirq<0x1>, 0x08, InterruptGate);

  Pointer ptr{.limit = sizeof(table), .base = (uint32_t)table};
  asm volatile("lidt %0" : : "m"(ptr));

  printk("IDT installed at ", (uint32_t)table, '\n');
}