diff options
Diffstat (limited to '0004-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch')
| -rw-r--r-- | 0004-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/0004-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch b/0004-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch new file mode 100644 index 0000000..b82ce17 --- /dev/null +++ b/0004-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch @@ -0,0 +1,85 @@ +From dd672eb4f207fcb2b26bafa0d61f118c3c11a479 Mon Sep 17 00:00:00 2001 +From: Likun Gao <Likun.Gao@amd.com> +Date: Fri, 2 Aug 2019 15:18:57 +0800 +Subject: drm/amdgpu: pin the csb buffer on hw init for gfx v8 + +Without this pin, the csb buffer will be filled with inconsistent +data after S3 resume. And that will causes gfx hang on gfxoff +exit since this csb will be executed then. + +Signed-off-by: Likun Gao <Likun.Gao@amd.com> +Tested-by: Paul Gover <pmw.gover@yahoo.co.uk> +Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++++++++++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 02955e6e9dd9..c21ef99cc590 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -1317,6 +1317,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) + return 0; + } + ++static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev) ++{ ++ int r; ++ ++ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); ++ if (unlikely(r != 0)) ++ return r; ++ ++ r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, ++ AMDGPU_GEM_DOMAIN_VRAM); ++ if (!r) ++ adev->gfx.rlc.clear_state_gpu_addr = ++ amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); ++ ++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); ++ ++ return r; ++} ++ ++static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev) ++{ ++ int r; ++ ++ if (!adev->gfx.rlc.clear_state_obj) ++ return; ++ ++ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); ++ if (likely(r == 0)) { ++ amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); ++ } ++} ++ + static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) + { + amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); +@@ -4777,6 +4810,10 @@ static int gfx_v8_0_hw_init(void *handle) + gfx_v8_0_init_golden_registers(adev); + gfx_v8_0_constants_init(adev); + ++ r = gfx_v8_0_csb_vram_pin(adev); ++ if (r) ++ return r; ++ + r = adev->gfx.rlc.funcs->resume(adev); + if (r) + return r; +@@ -4893,6 +4930,9 @@ static int gfx_v8_0_hw_fini(void *handle) + else + pr_err("rlc is busy, skip halt rlc\n"); + amdgpu_gfx_rlc_exit_safe_mode(adev); ++ ++ gfx_v8_0_csb_vram_unpin(adev); ++ + return 0; + } + +-- +cgit v1.2.1-1-g437b |