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authoraqua <aqua@iserlohn-fortress.net>2023-05-24 21:29:00 +0300
committeraqua <aqua@iserlohn-fortress.net>2023-05-24 21:29:29 +0300
commit050aa3ab70dd69d1ca8ffe94fd146039a0885550 (patch)
tree4002a7a0bb86580cc6a2adc2eee45891ee068540 /devices/uart
parentPlace compiled objects and dependencies in build/ (diff)
downloadkernel-050aa3ab70dd69d1ca8ffe94fd146039a0885550.tar.xz
Make code ANSI C compatible
Diffstat (limited to 'devices/uart')
-rw-r--r--devices/uart/uart_16550.c29
-rw-r--r--devices/uart/uart_16550.h56
2 files changed, 43 insertions, 42 deletions
diff --git a/devices/uart/uart_16550.c b/devices/uart/uart_16550.c
index 47a7fd3..0e19842 100644
--- a/devices/uart/uart_16550.c
+++ b/devices/uart/uart_16550.c
@@ -22,6 +22,7 @@ uart_putc(const FILE *self, char a)
int
uart_puts(const FILE *self, const char *string, int length)
{
+ int i;
int written = 0;
if (length == -1)
@@ -32,7 +33,7 @@ uart_puts(const FILE *self, const char *string, int length)
}
else
- for (int i = 0; i < length; ++i) {
+ for (i = 0; i < length; ++i) {
uart_putc(self, string[i]);
++written;
}
@@ -50,22 +51,22 @@ FILE uart_stream;
FILE *
uart_init(enum UART port)
{
- outb(0x00, port + 1); // Disable all interrupts
- outb(0x80, port + 3); // Enable DLAB (set baud rate divisor)
- outb(0x03, port + 0); // Set divisor to 3 (lo byte) 38400 baud
- outb(0x00, port + 1); // (hi byte)
- outb(0x03, port + 3); // 8 bits, no parity, one stop bit
- outb(0xc7, port + 2); // Enable FIFO, clear them, with 14-byte threshold
- outb(0x0b, port + 4); // IRQs enabled, RTS/DSR set
- outb(0x1e, port + 4); // Set in loopback mode, test the serial chip
- outb(0xae, port + 0); // Test serial chip (send byte 0xAE and check if serial
- // returns same byte)
+ outb(0x00, port + 1); /* Disable all interrupts */
+ outb(0x80, port + 3); /* Enable DLAB (set baud rate divisor) */
+ outb(0x03, port + 0); /* Set divisor to 3 (lo byte) 38400 baud */
+ outb(0x00, port + 1); /* (hi byte) */
+ outb(0x03, port + 3); /* 8 bits, no parity, one stop bit */
+ outb(0xc7, port + 2); /* Enable FIFO, clear them, with 14-byte threshold */
+ outb(0x0b, port + 4); /* IRQs enabled, RTS/DSR set */
+ outb(0x1e, port + 4); /* Set in loopback mode, test the serial chip */
+ outb(0xae, port + 0); /* Test serial chip (send byte 0xAE and check if serial */
+ /* returns same byte) */
- // Check if serial is faulty (i.e: not same byte as sent)
+ /* Check if serial is faulty (i.e: not same byte as sent) */
if (inb(port + 0) != 0xae) { return NULL; }
- // If serial is not faulty set it in normal operation mode
- // (not-loopback with IRQs enabled and OUT#1 and OUT#2 bits enabled)
+ /* If serial is not faulty set it in normal operation mode */
+ /* (not-loopback with IRQs enabled and OUT#1 and OUT#2 bits enabled) */
outb(0x0f, port + 4);
uart_stream.id = port;
uart_stream.putc = &uart_putc;
diff --git a/devices/uart/uart_16550.h b/devices/uart/uart_16550.h
index f8e1931..176dea2 100644
--- a/devices/uart/uart_16550.h
+++ b/devices/uart/uart_16550.h
@@ -8,42 +8,42 @@ int uart_puts(const FILE *self, const char *string, int length);
void uart_flush(__attribute__((unused)) const FILE *self);
enum uart_16550_offset {
- Data = 0, // read from receive buffer / write to transmit buffer | BaudDiv_l
- InterruptControl = 1, // interrupt enable | BaudDiv_h
- FifoControl = 2, // interrupt ID and FIFO control
- LineControl = 3, // most significant bit is the DLAB
+ Data = 0, /* read from receive buffer / write to transmit buffer | BaudDiv_l */
+ InterruptControl = 1, /* interrupt enable | BaudDiv_h */
+ FifoControl = 2, /* interrupt ID and FIFO control */
+ LineControl = 3, /* most significant bit is the DLAB */
ModemControl = 4,
LineStatus = 5,
ModemStatus = 6,
Scratch = 7,
};
-// Line Control
-// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-// |dla| | parity | s | data |
+/* Line Control
+ * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+ * |dla| | parity | s | data | */
enum LineControl {
- d5bit = 0x00, // 0000 0000 data bits
- d6bit = 0x01, // 0000 0001
- d7bit = 0x02, // 0000 0010
- d8bit = 0x03, // 0000 0011
- // none = 0b00000000, // parity bits
- odd = 0x08, // 0000 1000
- even = 0x18, // 0001 1000
- mark = 0x28, // 0010 1000
- space = 0x38, // 0011 1000
- // s1bit = 0b00000000, // stop bits
- s2bit = 0x04, // 0000 0100 1.5 for 5bit data; 2 otherwise
- dlab = 0x80 // 1000 0000 divisor latch access bit
+ d5bit = 0x00, /* 0000 0000 data bits */
+ d6bit = 0x01, /* 0000 0001 */
+ d7bit = 0x02, /* 0000 0010 */
+ d8bit = 0x03, /* 0000 0011 */
+ /* none = 0b00000000, // parity bits */
+ odd = 0x08, /* 0000 1000 */
+ even = 0x18, /* 0001 1000 */
+ mark = 0x28, /* 0010 1000 */
+ space = 0x38, /* 0011 1000 */
+ /* s1bit = 0b00000000, // stop bits */
+ s2bit = 0x04, /* 0000 0100 1.5 for 5bit data; 2 otherwise */
+ dlab = 0x80 /* 1000 0000 divisor latch access bit */
};
-// Line Status Register
+/* Line Status Register */
enum LineStatus {
- DR = (1 << 0), // data ready: see if there is data to read
- OE = (1 << 1), // overrun error: see if there has been data lost
- PE = (1 << 2), // parity error: see if there was error in transmission
- FE = (1 << 3), // framing error: see if a stop bit was missing
- BI = (1 << 4), // break indicator: see if there is a break in data input
- THRE = (1 << 5), // transmitter holding register empty: see if transmission buffer is empty
- TEMT = (1 << 6), // transmitter empty: see if transmitter is not doing anything
- ERRO = (1 << 7), // impending error: see if there is an error with a word in the input buffer
+ DR = (1 << 0), /* data ready: see if there is data to read */
+ OE = (1 << 1), /* overrun error: see if there has been data lost */
+ PE = (1 << 2), /* parity error: see if there was error in transmission */
+ FE = (1 << 3), /* framing error: see if a stop bit was missing */
+ BI = (1 << 4), /* break indicator: see if there is a break in data input */
+ THRE = (1 << 5), /* transmitter holding register empty: see if transmission buffer is empty */
+ TEMT = (1 << 6), /* transmitter empty: see if transmitter is not doing anything */
+ ERRO = (1 << 7), /* impending error: see if there is an error with a word in the input buffer */
};