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author | aqua <aqua@iserlohn-fortress.net> | 2022-11-08 17:19:45 +0200 |
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committer | aqua <aqua@iserlohn-fortress.net> | 2022-11-08 17:54:13 +0200 |
commit | dbdaa77fb5924b4b9e6b374a44ef76481a38d3d2 (patch) | |
tree | abd4daf428532ac026a538e20138907b36c795c3 /devices/uart_16550.c | |
parent | Add python-sphinx docs (diff) | |
download | kernel-dbdaa77fb5924b4b9e6b374a44ef76481a38d3d2.tar.xz |
Add FILE struct
Diffstat (limited to 'devices/uart_16550.c')
-rw-r--r-- | devices/uart_16550.c | 78 |
1 files changed, 43 insertions, 35 deletions
diff --git a/devices/uart_16550.c b/devices/uart_16550.c index 22f33ad..40ac594 100644 --- a/devices/uart_16550.c +++ b/devices/uart_16550.c @@ -1,4 +1,5 @@ #include "uart_16550.h" +#include <stddef.h> #include <sys/io.h> enum uart_16550_offset { @@ -43,67 +44,74 @@ enum LineStatus { }; int -uart_init(enum UART port) -{ - outb(0x00, port + 1); // Disable all interrupts - outb(0x80, port + 3); // Enable DLAB (set baud rate divisor) - outb(0x03, port + 0); // Set divisor to 3 (lo byte) 38400 baud - outb(0x00, port + 1); // (hi byte) - outb(0x03, port + 3); // 8 bits, no parity, one stop bit - outb(0xc7, port + 2); // Enable FIFO, clear them, with 14-byte threshold - outb(0x0b, port + 4); // IRQs enabled, RTS/DSR set - outb(0x1e, port + 4); // Set in loopback mode, test the serial chip - outb(0xae, port + 0); // Test serial chip (send byte 0xAE and check if serial - // returns same byte) - - // Check if serial is faulty (i.e: not same byte as sent) - if (inb(port + 0) != 0xae) { - return 1; - } - - // If serial is not faulty set it in normal operation mode - // (not-loopback with IRQs enabled and OUT#1 and OUT#2 bits enabled) - outb(0x0f, port + 4); - return 0; -} - -int uart_thre(enum UART port) { return inb(port + LineStatus) & THRE; } void -uart_write(enum UART port, char a) +uart_write(const FILE *self, char a) { - while (uart_thre(port) == 0) - ; - outb(a, port); + while (uart_thre(self->id) == 0) {} + outb(a, self->id); if (a == '\n') { - while (uart_thre(port) == 0) - ; - outb('\r', port); + while (uart_thre(self->id) == 0) {} + outb('\r', self->id); } } int -uart_puts(enum UART port, const char *string, int length) +uart_puts(const FILE *self, const char *string, int length) { int written = 0; if (length == -1) while (*string != '\0') { - uart_write(port, *string); + uart_write(self, *string); ++string; ++written; } else for (int i = 0; i < length; ++i) { - uart_write(port, string[i]); + uart_write(self, string[i]); ++written; } return written; } + +void +uart_flush(const FILE *self) +{ +} + +FILE uart_stream; + +FILE * +uart_init(enum UART port) +{ + outb(0x00, port + 1); // Disable all interrupts + outb(0x80, port + 3); // Enable DLAB (set baud rate divisor) + outb(0x03, port + 0); // Set divisor to 3 (lo byte) 38400 baud + outb(0x00, port + 1); // (hi byte) + outb(0x03, port + 3); // 8 bits, no parity, one stop bit + outb(0xc7, port + 2); // Enable FIFO, clear them, with 14-byte threshold + outb(0x0b, port + 4); // IRQs enabled, RTS/DSR set + outb(0x1e, port + 4); // Set in loopback mode, test the serial chip + outb(0xae, port + 0); // Test serial chip (send byte 0xAE and check if serial + // returns same byte) + + // Check if serial is faulty (i.e: not same byte as sent) + if (inb(port + 0) != 0xae) { return NULL; } + + // If serial is not faulty set it in normal operation mode + // (not-loopback with IRQs enabled and OUT#1 and OUT#2 bits enabled) + outb(0x0f, port + 4); + uart_stream.id = port; + uart_stream.putc = &uart_write; + uart_stream.puts = &uart_puts; + uart_stream.flush = &uart_flush; + return &uart_stream; +} |