1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
#pragma once
#include "uart.h"
int uart_thre(unsigned short port);
void uart_putc(const FILE *self, char a);
int uart_puts(const FILE *self, const char *string, int length);
void uart_flush(__attribute__((unused)) const FILE *self);
enum uart_16550_offset {
Data = 0, /* read from receive buffer / write to transmit buffer | BaudDiv_l */
InterruptControl = 1, /* interrupt enable | BaudDiv_h */
FifoControl = 2, /* interrupt ID and FIFO control */
LineControl = 3, /* most significant bit is the DLAB */
ModemControl = 4,
LineStatus = 5,
ModemStatus = 6,
Scratch = 7
};
/* Line Control
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* |dla| | parity | s | data | */
enum LineControl {
d5bit = 0x00, /* 0000 0000 data bits */
d6bit = 0x01, /* 0000 0001 */
d7bit = 0x02, /* 0000 0010 */
d8bit = 0x03, /* 0000 0011 */
/* none = 0b00000000, // parity bits */
odd = 0x08, /* 0000 1000 */
even = 0x18, /* 0001 1000 */
mark = 0x28, /* 0010 1000 */
space = 0x38, /* 0011 1000 */
/* s1bit = 0b00000000, // stop bits */
s2bit = 0x04, /* 0000 0100 1.5 for 5bit data; 2 otherwise */
dlab = 0x80 /* 1000 0000 divisor latch access bit */
};
/* Line Status Register */
enum LineStatus {
DR = (1 << 0), /* data ready: see if there is data to read */
OE = (1 << 1), /* overrun error: see if there has been data lost */
PE = (1 << 2), /* parity error: see if there was error in transmission */
FE = (1 << 3), /* framing error: see if a stop bit was missing */
BI = (1 << 4), /* break indicator: see if there is a break in data input */
THRE = (1 << 5), /* transmitter holding register empty: see if transmission buffer is empty */
TEMT = (1 << 6), /* transmitter empty: see if transmitter is not doing anything */
ERRO = (1 << 7) /* impending error: see if there is an error with a word in the input buffer */
};
|
