diff options
| author | mseaborn@chromium.org <mseaborn@chromium.org@4c0a9323-5329-0410-9bdc-e9ce6186880e> | 2013-05-08 02:37:15 +0000 |
|---|---|---|
| committer | mseaborn@chromium.org <mseaborn@chromium.org@4c0a9323-5329-0410-9bdc-e9ce6186880e> | 2013-05-08 02:37:15 +0000 |
| commit | b45b97b2fd735eea5f0e5824b0a48132ccafd88e (patch) | |
| tree | b9335342914d6f9452fa2526f98b7834467f67b7 /src/processor | |
| parent | Add MD_OS_NACL platform_id value for identifying NaCl minidumps (diff) | |
| download | breakpad-b45b97b2fd735eea5f0e5824b0a48132ccafd88e.tar.xz | |
Make x86-64 stack walking work for Native Client minidumps
For NaCl, a stack walker should ignore the top 32 bits of %rip, %rsp
and %rbp, otherwise it will try to read from %r15-extended stack
addresses and look up symbol info for %r15-extended code addresses,
which will fail.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3424
TEST=tested manually with a NaCl minidump
Review URL: https://breakpad.appspot.com/591002
git-svn-id: http://google-breakpad.googlecode.com/svn/trunk@1173 4c0a9323-5329-0410-9bdc-e9ce6186880e
Diffstat (limited to 'src/processor')
| -rw-r--r-- | src/processor/stackwalker_amd64.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/processor/stackwalker_amd64.cc b/src/processor/stackwalker_amd64.cc index 656af183..737a2496 100644 --- a/src/processor/stackwalker_amd64.cc +++ b/src/processor/stackwalker_amd64.cc @@ -40,6 +40,7 @@ #include "google_breakpad/processor/memory_region.h" #include "google_breakpad/processor/source_line_resolver_interface.h" #include "google_breakpad/processor/stack_frame_cpu.h" +#include "google_breakpad/processor/system_info.h" #include "processor/cfi_frame_info.h" #include "processor/logging.h" #include "processor/stackwalker_amd64.h" @@ -222,6 +223,16 @@ StackFrame* StackwalkerAMD64::GetCallerFrame(const CallStack* stack) { if (!new_frame.get()) return NULL; + if (system_info_->os_short == "nacl") { + // Apply constraints from Native Client's x86-64 sandbox. These + // registers have the 4GB-aligned sandbox base address (from r15) + // added to them, and only the bottom 32 bits are relevant for + // stack walking. + new_frame->context.rip = static_cast<uint32_t>(new_frame->context.rip); + new_frame->context.rsp = static_cast<uint32_t>(new_frame->context.rsp); + new_frame->context.rbp = static_cast<uint32_t>(new_frame->context.rbp); + } + // Treat an instruction address of 0 as end-of-stack. if (new_frame->context.rip == 0) return NULL; |